JPH0719165Y2 - マルチチップ構造 - Google Patents

マルチチップ構造

Info

Publication number
JPH0719165Y2
JPH0719165Y2 JP16410488U JP16410488U JPH0719165Y2 JP H0719165 Y2 JPH0719165 Y2 JP H0719165Y2 JP 16410488 U JP16410488 U JP 16410488U JP 16410488 U JP16410488 U JP 16410488U JP H0719165 Y2 JPH0719165 Y2 JP H0719165Y2
Authority
JP
Japan
Prior art keywords
chip
bumps
bump
chips
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP16410488U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0284347U (en]
Inventor
義一 大江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16410488U priority Critical patent/JPH0719165Y2/ja
Publication of JPH0284347U publication Critical patent/JPH0284347U/ja
Application granted granted Critical
Publication of JPH0719165Y2 publication Critical patent/JPH0719165Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP16410488U 1988-12-19 1988-12-19 マルチチップ構造 Expired - Lifetime JPH0719165Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16410488U JPH0719165Y2 (ja) 1988-12-19 1988-12-19 マルチチップ構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16410488U JPH0719165Y2 (ja) 1988-12-19 1988-12-19 マルチチップ構造

Publications (2)

Publication Number Publication Date
JPH0284347U JPH0284347U (en]) 1990-06-29
JPH0719165Y2 true JPH0719165Y2 (ja) 1995-05-01

Family

ID=31449420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16410488U Expired - Lifetime JPH0719165Y2 (ja) 1988-12-19 1988-12-19 マルチチップ構造

Country Status (1)

Country Link
JP (1) JPH0719165Y2 (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302212A (ja) 2008-06-11 2009-12-24 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
JP5678978B2 (ja) * 2013-03-11 2015-03-04 富士通セミコンダクター株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0284347U (en]) 1990-06-29

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